An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing power consumption in semiconductor devices. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) are particularly well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decrease, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, with a depth on the order of 1000 Å or less, are generally required for acceptable performance in short channel devices.
Silicon-on-insulator (SOI) technology allows the formation of high-speed, shallow-junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.
In a SOI substrate, a buried oxide (BOX) film made of silicon oxide is formed on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods for fabricating such SOI substrates are known. One such method is Separation-by-Implanted Oxygen (SIMOX), wherein oxygen is ion implanted into a single crystal silicon substrate to form a buried oxide (BOX) film.
Another method of forming a SOI substrate is wafer bonding, wherein two semiconductor substrates with silicon oxide surface layers are bonded together at the silicon oxide surfaces to form a BOX layer between the two semiconductor substrates.
Another SOI technique is Smart Cut®, which also involves bonding semiconductor substrates through oxide layers. In the Smart Cut® method, one of the semiconductor substrates is implanted with hydrogen ions prior to bonding. The hydrogen ion implants subsequently allows the hydrogen ion implanted substrate to be split from the bonded substrates leaving behind a thin layer of silicon on the surface.
Semiconductor device performance can be further enhanced by the selection of silicon layers with certain crystal plane orientations, which facilitate hole or electron flow. For example, the performance of P-type MOSFETs (PMOSFETs) can be improved if they are fabricated on a (110) silicon surface, with the gates oriented so that the holes flow in the (110)/<110> direction. The mobility of holes flowing in the (110)/<110> direction is more than twice as high as that of holes flowing in the conventional (100)/<110> direction. Unfortunately, on the (110) surface holes traveling at right angles to the (110)/<110> direction flow in the (110)/<100> direction. Hole mobility in the (110)/<100> direction is only two-thirds that of holes flowing in the (110)/<110> direction. In addition, electron mobility in the (110) plane is much lower than that in the conventional (100) plane.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.